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Research Areas:
VLSI Circuit, Power Supply Noise, Clock Gating, Wireline Communication, Optical Logic
Research/Project title: Device Circuit Co-Design
Year of Joining: 2020
Status: Current
Research/Project title: Optical Reversible Circuit
Year of Joining: 2019
Co-Supervisor: Dr. Sanjeev K Metya
Status: Current
Research/Project title: Adaptive Power Gating Circuit
Year of Joining: 2022
Co-Supervisor: Dr. Alak Majumder
Status: Current
Research/Project title: Optical Arithmetic Circuit
Year of Joining: 2020
Status: Current
Research/Project title: Power Gating Methodologies
Year of Joining: 2021
Status: Current
Research/Project title: Embedding of Variable Frequency Clock & Clock Gating to Mitigate Power Supply Noise in Silicon Chip
Year of Joining: 2016
Year of Complete: 2020
Co-Supervisor: Dr. Tushar Dhabal Das
Current Placement: Assistant Professor, Amrita Vishwa Vidyapeetham
Status: Completed
Research/Project title: Variation Tolerant Design of PLL Constituents for High Speed Application
Year of Joining: 2016
Year of Complete: 2020
Co-Supervisor: Dr. Alak Majumder
Current Placement: Staff Engineer, Memsmart Pvt. Ltd. Bangalore
Status: Completed
Research/Project title: Design of Power Efficient CDR Circuit Constituents for Serial Data Communication
Year of Joining: 2016
Year of Complete: 2020
Co-Supervisor: Dr. Swarnendu K Chakraborty
Current Placement: Assistant Professor, CV Raman Global University, Bhubaneswar
Status: Completed
Research/Project title: Digital VLSI Circuit
Year of Joining: 2020
Year of Complete: 2022
Status: Completed
Research/Project title: Digital VLSI Circuit
Year of Joining: 2020
Year of Complete: 2022
Status: Completed
Research/Project title: An Design Methodology for Frequency Multiplication by Factor-N
Year of Joining: 2017
Year of Complete: 2019
Status: Completed
Research/Project title: Current Mode Mux-Latch Based Serializer Design for Power Efficient On-Chip Data Links
Year of Joining: 2016
Year of Complete: 2018
Status: Completed
Research/Project title: A New Circuit Configuration of Power Efficient SRAM
Year of Joining: 2016
Year of Complete: 2018
Status: Completed
Research/Project title: On-Chip Power Supply Noise Mitigation by Steering the Switching Pattern of Clock Tree
Year of Joining: 2016
Year of Complete: 2018
Status: Completed
Research/Project title: Variable Frequency Generation for Mitigating PSN of Silicon Chip
Year of Joining: 2016
Year of Complete: 2018
Status: Completed
Research/Project title: Process-Voltage-Temperature Aware Configuration of Gated Clock for Low Power Sequential System
Year of Joining: 2016
Year of Complete: 2018
Status: Completed
Research/Project title: Low Swing Signalling Driver & Receiver Circuit
Year of Joining: 2016
Year of Complete: 2018
Status: Completed
Research/Project title: Current Mode Design of Mux-Latch Architecture for Gigascale Serializer Interface Circuit
Year of Joining: 2015
Year of Complete: 2017
Status: Completed
Research/Project title: Design of Gated Clock Tree Circuit to Yield a Current Profile for Mitigating Power Supply Noise of Integrated CPU Chip​
Year of Joining: 2015
Year of Complete: 2017
Status: Completed
Research/Project title: Design Approaches of Operational Transconductance Amplifier Using Positive Feedback Load for Filter Applications​
Year of Joining: 2015
Year of Complete: 2017
Status: Completed
Research/Project title: Synthesis and Verification of a New OKFDD approach for Line Minimization of Reversible Circuits
Year of Joining: 2015
Year of Complete: 2017
Status: Completed
Research/Project title: Majority Function and Adiabatic Principle Based Design Approach for Low Power VLSI
Year of Joining: 2014
Year of Complete: 2016
Status: Completed
Research/Project title: Development of a Biometric Hardware Module Incorporating NFC for Peer-to- peer Money Transfer & Identity Virtualization
Year of Joining: 2014
Year of Complete: 2016
Status: Completed
Research/Project title: Hardware/Software Co-Design using NFC Enabled Smartphone for Biometric P2P Payment and Identity Virtualization
Year of Joining: 2014
Year of Complete: 2016
Status: Completed
Research/Project title: Synthesis & Realization of Optimized Reversible Logic Circuits for Novel ALU Design
Year of Joining: 2013
Year of Complete: 2015
Status: Completed
