2022

1. J Kandpal, TR Pokhrel, S Saini, A Majumder "A Variation Resilient Keeper Design for High Performance Domino Logic Applications", Integration, The VLSI Journal, Elsevier, , 2022.[SCI/SCIE, Q3]

2. M Kumar, A Majumder, AJ Mondal, A Raychowdhury, BK Bhattacharyya "A low power and PVT variation tolerant mux-latch for serializer interface and on-chip serial link", Integration, The VLSI Journal, Elsevier, , 2022.[SCI/SCIE, Q3]

3. M Kumar, A Majumder, AJ Mondal "Simulation and Analysis of a Digitally Controlled Differential Delay Circuit Under Process, Voltage, Temperature and Noise due to Injection of High Current", Journal of Circuits, Systems and Computers, World Scientific Publishers, , 2022.[SCI/SCIE, Q3]

4. TR Pokhrel, A Majumder "Impact of Work Function Engineering on Strained Silicon Based Double Gated Junction-less Transistor", Silicon, Springer, , 2022.[SCI/SCIE, Q2]

5. S. Awasthi, B. Chowdhury, Z. Haider, J. Ali, P. Yupapin, S.K. Metya, A. Majumder "Exploring Reversible NOR from 4*4 Modified Fredkin Gate and its Optical Mapping using LiNbO3 Based MZI", Journal Journal of Computational Electronics, Springer, , 2022.[SCI/SCIE, Q3]

2021

1. S. Awasthi, B. Chowdhury, Z. Haider, J. Ali, P. Yupapin, S.K. Metya, A. Majumder "Optical Configuration of N:2^N Reversible Decoder using LiNbO3 based Mach-Zehnder Interferometer", Applied Optics, OSA, , 2021.[SCI/SCIE, Q2]

2. P. Bhattacharjee, B.K. Bhattacharyya, A. Majumder "Vector Controlled Delay Cell with Nearly Identical Rise/Fall Time for Processor Clock Application", Informacije MIDEM - Journal of Microelectronics, Electronic Components and Materials, Slovenia, , 2021.[SCI/SCIE, Q4]

3. P. Bhattacharjee, P. Rana, B.K. Bhattacharyya, A. Majumder "Clock Gated Variable Frequency Signaling to Alleviate Power Supply Noise in a Packaged IC", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, , 2021.[SCI/SCIE, Q1]

4. S.K. Saw, U. Nanda, N. Laskar, A. Majumder "A Dynamic Current Mode Design Approach of 2/3 Prescaler for Phase Locked Loop Application", Analog Integrated Circuits and Signal Processing, Springer, , 2021.[SCI/SCIE, Q3]

2020

1. P Bhattacharjee, BK Bhattacharyya, A Majumder "A Vector Controlled Variable Delay Circuit to Develop Near Symmetric Output Rise/Fall Time", Circuits, Systems, and Signal Processing, Springer, , 2020.

2. S Awasthi, A Biswas, SK Metya, A Majumder "Optical Configuration of Modified Fredkin Gate using Lithium Niobate based Mach Zehnder Interferometer", Applied Optics, OSA, , 2020.

3. M Maiti, A Majumder, S Chakrabartty, H Song, BK Bhattacharyya "Modeling and Analysis of a Hybrid CS-CMOS Ring VCO with Wide Tuning Range", Microelectronics Journal, Elsevier, , 2020.

4. A Tarafdar, UK Bera, BK Bhattacharyya, A Majumder "Mathematical Understanding of a Data Reconstruction Methodology in Point-to-point Interconnect", IEEE VLSI Circuit & System Letter, vol. 6 , issue 1, 2020.

2019

1. M Maiti, A Paul, SK Saw, A Majumder "Passive Element free Variation Aware Decision Circuit for 40 Gb/s CDR Application", Microsystem Technologies, Springer, , 2019.

2. M. Maiti, S.K. Saw, A.J. Mondal, A. Majumder "A Hybrid Design Approach of PVT Tolerant, Power Efficient Ring VCO", Ain Shams Engineering Journal, Elsevier, , 2019.

3. SK Saw, SK Yadav, M Maiti, AJ Mondal, A Majumder "A Design Approach of Higher Oscillation VCO made of CS Amplifier with Varying Active Load", Microsystem Technologies, Springer, , 2019.

4. M. Maiti, S.K. Saw, V. Nath, A. Majumder "A Power Efficient PFD-CP Architecture for High Speed Clock and Data Recovery Application", Microsystem Technologies, Springer, , 2019.

5. P. Bhattacharjee, D. Sarkar, A. Majumder "A Variation Tolerant Data Dependent Clock Gating Approach for PSN Attenuated Low Power Digital IC", Ain Shams Engineering Journal, Elsevier, , 2019.

6. SK Saw, M Maiti, P Meher, A Majumder "PVT Aware Design of a Dead-Zone Free High Speed Phase Frequency Detector in 90nm CMOS", Recent Advances in Electrical & Electronic Engineering, vol. 12 , issue 1, 2019.

2018

1. A. Majumder, M. Das, S.K. Saw, A.J. Mondal, and B.K. Bhattacharyya "Variation Aware Design of 50-Gbit/s, 5.027-fJ/bit Serializer Using Latency Combined Mux-Dual Latch for Inter-Chip Communication", IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66(3), pp. 1231-1244, 2018.

2. A. Majumder, M. Das, S.K. Saw, B.K. Bhattacharyya "“An Energy Efficient PVT Aware Novel CML-TG based Mux-Latch Circuit Serializes High Rate Data”", Microsystem Technologies, Springer, , 2018.

3. P. Bhattacharjee, A. Majumder ""A Variation Aware Robust Gated Flip-Flop for Power Constrained FSM Application”", Journal of Circuit, System and Computers, World Scientific Publishers, vol. Vol-28 , issue No-07, 2018.

4. A. Majumder, B. Nath, M. Das, B.K. Bhattacharyya "“A Variation Tolerant Current Mode Low Swing Signaling Approach for Gigascale On-chip Interface Circuit”", AEU-International Journal of Electronics and Communications, Elsevier, vol. 93, 2018.

5. S.K. Saw, P. Das, M. Maiti, A. Majumder "A Power Efficient Charge Pump Circuit Configuration for Fast Locking PLL Application", Microsystem Technologies, Springer, , 2018.

6. A. Majumder, P. Bhattacharjee, T.D. Das "A Novel Gating Approach to Alleviate Power and Ground Noise in Silicon Chip", Journal of Circuits, Systems and Computers, World Scientific Publishers, vol. 27 , issue 9, 2018.

7. S. Rambabu, A. Majumder "Gain Improved Design of Cascode OTA using PMOS Based Positive Feedback", IEEE VLSI Circuit and System Letters, vol. 4 , issue 2, 2018.

8. A. Majumder, P. Bhattacharjee "Variation Aware Intuitive Clock Gating to Mitigate On-chip Power Supply Noise", International Journal of Electronics, Taylor & Francis, vol. 105 , issue 7, 2018.

9. N. Laskar, S. Debnath, A. Majumder and B.K. Bhattacharyya "A New Current Profile Determination Methodology Incorporating Gating Logic to Minimize the Noise of CPU Chip by 40%", Journal of Circuit, System and Computers, World Scientific Publishers, vol. 27 , issue 3, 2018.

10. P. Bhattcharjee, A.J. Mondal, A. Majumder "A graphical approach to design and optimization of MOS amplifier", Journal of Engineering Science and Technology (JESTEC), vol. 13 , issue 1, 2018.

2017

1. A. Majumder "Gated Clock Tree Circuit to Reduce the Noise in Silicon Chip", Journal of Low Power Electronics, American Scientific Publisher, vol. 13 , issue 4, 2017.

2. A. Majumder, A.J. Mondal, B.K. Bhattacharyya "A 65nm Design of 0.6V/8.98µW PVT Aware Dynamic Analog Comparator for High Speed Data Reconstruction Applications", ASP Journal of Low Power Electronics, vol. 13 , issue 3, 2017.

3. B. Nath, A. Majumder, M. Das, A.J. Mondal, P. Chakraborty, B.K. Bhattacharyya "Voltage Keeper Based 28.27µW New Frequency Divider Circuit in 90nm Technology for Gigascale SerDes Application", IEEE VLSI Circuit and System Letters, vol. 3 , issue 2, 2017.

4. A. J. Mondal, A. Majumder, B.K. Bhattacharyya, P. Chakraborty "A Process Aware Delay Circuit with Reduce Impact of Input Switching at GHz Frequencies", IEEE VLSI Circuit and System Letters, vol. 3 , issue 2, 2017.

5. A. J. Mondal, A. Majumder, B.K. Bhattacharyya "Mathematical Formulation to Design and Implementation of a Low voltage swing transceiver circuit", Integration, The VLSI Journal; Elsevier, vol. 58, 2017.

6. A. Majumder, A.J. Mondal, B.K. Bhattacharyya "Threshold Adjustment of Receiver Chip to Achieve a Data Rate > 66Gbit/s in Point-to-point Interconnect", Integration, The VLSI Journal; Elsevier, vol. 58, 2017.

7. A. Majumder, B.K. Bhattacharyya "Reconstruction of single pulse originally having 40psec width coming from a lossy and noisy channel in point to point interconnect", Turkish Journal of Electrical Engineering and Computer Sciences, vol. 25 , issue 03, 2017.

8. J. Goswami, S. Ghosh, R. Shrivastawa, S.P. Mohanty and B.K. Bhattacharyya "Pay-cloak: A Biometric Back Cover for Smartphones: Facilitating Secure Contactless Payments and Identity Virtualization at Low Cost to the End Users", IEEE Consumer Electronics Magazine, vol. 6 , issue 2, 2017.

9. S. Ghosh, A. Majumder, J. Goswami, A. Kumar, S.P. Mohanty, B.K. Bhattacharyya "Swing-Pay: One Card Meets All User Payment and Identity Needs: A Digital Card Module using NFC and Biometric Authentication for Peer-to-Peer Payment", IEEE Consumer Electronics Magazine, vol. 6 , issue 1, 2017.

2016

1. S.K. Singh, A.J. Mondal, A. Majumder "Generation and Performance Evaluation of Reconfigurable Fault Tolerant Routing Algorithm for 2D Mesh NOC", Procedia Computer Science, Elsevier, vol. 57, 2016.

2. A. Majumder, B. Chowdhury, P.L. Singh, R. Rai "Synthesis & Realization of N-bit Reversible Register File used in Bus Organization of Processor Architecture", Procedia Computer Science, Elsevier, vol. 57, 2016.

3. A. Majumder, P.L. Singh, B. Chowdhury, A.J. Mondal, V. Anand "Efficient Design & Analysis of N-bit Reversible Shift Registers", Procedia Computer Science, Elsevier, , 2016.

4. P.L. Singh, A. Majumder, B. Chowdhury, A.J. Mondal, T.S. Shekawat "Reducing Delay & Quantum Cost in the Novel Design of Reversible Memory Elements", Procedia Computer Science, Elsevier, vol. 57, 2016.

2015

1. A. Majumder, B. Nath, D. Sarkar, M. Das "Cycle in Conventional Combinational Circuits: A Comprehensive Survey", International Journal Advanced Science & Technology, Korea, vol. 80, 2015.

2. A. Kar, A. Majumder "A 43µwatt 3-bit Flash ADC designed with TMCC and Bit Referenced Encoder in 180 nm CMOS Technology", International Journal Advanced Science & Technology, Korea, vol. 79, 2015.