2024

1. Lukram Dhanachandra Singh, Preetisudha Meher "Dual Arbiter PUF with Shift Register based TRNG on Basys-3 FPGA board and its performance analysis on Uniqueness, Reliability and Randomness", International Journal of Intelligent Systems and Applications in Engineering, Elsevier, vol. Accepted, 2024.[Scopus, Q3]

2. Shanvendra Rai, Rituparna Paul, Subhasish Banerjee, Preetisudha Meher, Gulab Sah "A Combined Approach of PUF and Physiological Data for Mutual Authentication and Key Agreement in WMSN", Journal of Grid Computing Springer, vol. 22 , issue 23, pp. 1-22, 2024. (https://doi.org/10.1007/s10723-023-09731-5)[SCI/SCIE, Q1]

2023

1. Hindol Bhattacharjee, Anup Dey, Preetisudha Meher "Modeling and Simulation of Recess Gate AlGaN/GaN HEMT Device with GaN Buried Layer for Improvising Performance", Microsystem Technologies, Springer, vol. Accepted, 2023.[SCI/SCIE, Q2]

2. Madhusmita Dash, Preetisudha Meher, Siddharth Satpathy "Codon usage in conserved sites is more biased compared to variable sites in the SARS-CoV-2 genome", International Journal of Bioinformatics Research and Applications, Inderscience Journals, vol. Accepted, 2023.[Scopus, Q3]

2020

1. Sapna Rani Ghimiray, Preetisudha Meher, Pranab Kishor Dutta "An improved charge?sharing elimination pseudo?domino logic", International Journal of Circuit Theory and Applications, Wiley, vol. 48 , issue 8, pp. 1346-1362, 2020. (DOI: https://doi.org/10.1002/cta.2798)

2019

1. Suraj Kumar Saw, Madhusudan Maiti, Preetisudha Meher, Alak Majumder "PVT Aware Design of a Dead-Zone Free High Speed Phase Frequency Detector in 90nm CMOS", Recent Advances in Electrical & Electronic Engineering, vol. Volume 13 , issue Issue 4, pp. 516-530, 2019. (DOI - 10.2174/2352096512666190314111752)

2. Lukram Dhanachandra Singh, Preetisudha Meher "Advancement of blockchain security solution with FPGA", International Journal of Advanced Science and Technology, Elsevier, vol. 28 , issue 3, pp. 276-283, 2019. (http://sersc.org/journals/index.php/IJAST/article/view/331)

3. Umesh Gupta, Dr. Preetisudha Meher "Evaluation of target tracking approaches using infrared imagery", International Journal of Advanced Science and Technology, Elsevier, vol. 28 , issue 3, pp. 284-292, 2019. (http://sersc.org/journals/index.php/IJAST/article/view/334)

2018

1. Payali Das and Preetisudha Meher "Low Power Fast Locking Charge Pump Design for PLL Application ", Low Power Fast Locking Charge Pump Design for PLL Application, vol. 14 , issue Special Issue, pp. 1939-1948, 2018. (https://www.jardcs.org/backissues/abstract.php?archiveid=6702)

2. Rashmita Baruah, Preetisudha Meher "Efficient Implementation of Multiplier Using CORDIC and Vedic Mathematics", JARDCS, vol. 15 , issue Special Issue, pp. 745-751, 2018. (https://www.jardcs.org/backissues/abstract.php?archiveid=6779)

3. Sapna Rani Ghimiray Preetisudha Meher Pranab Kishore Dutta "Ultra-Low Power, Noise Immune Stacked- double stage Clocked-inverter domino technique for Ultra Deep Submicron Technology", International Journal of Circuit Theory and Applications, Wiley, vol. 46 , issue 11, pp. 1953-1967, 2018. (https://doi.org/10.1002/cta.2524)

2017

1. Sapna Rani Ghimiray, Preetisudha Meher and Manish Kumar "A Leakage-Tolerant 16 – Bit Comparator Using Lector Technique Based Footless Domino Logic Circuit", IOP Conference Series: Materials Science and Engineering, Springer, vol. 225, pp. 1-9, 2017. (https://doi.org/10.1088/1757-899X/225/1/012139)

2014

1. Preetisudha Meher, Kamalakanta Mahapatra "Modifications in CMOS Dynamic Logic Style: A Review Paper", Journal of the Institution of Engineers, Springer, vol. 96 , issue 4, pp. 391-399, 2014. (DOI: 10.1007/s40031-014-0150-8)

2013

1. Preetisudha Meher, Kamalakanta Mahapatra "High-Speed and Low-Power Dynamic Logic Style ", International Journal of VLSI and Embedded Systems (IJVES), Interscience, vol. 4 , issue 3, pp. 177-182, 2013. (https://www.interscience.in/ijcct/vol4/iss3/6)