Dr. Preetisudha Meher

Assistant Professor

Dr. Preetisudha Meher

Asst. Professor

Dept. Of Electronics and Communication Engineering,

National Institute of Technology, Yupia,

Arunachal Pradesh

Permanent Address: S3H1-23, RDA Colony, Chhend, Rourkela, Odisha, PIN- 769015

Email: preetisudha1@gmail.com

Mobile No.: +91-9040544300, 9438823600

EDUCATION

Ph.D. Electronics and communication Engineering, National Institute of Technology (NIT), Rourkela, Odisha, INDIA (From Sep. 2009 to Apr. 2015) (Awarded on 22nd Apr. 2015)

Thesis Title: Design and analysis of improved domino logic with noise tolerance and high performance.

Supervisor: Prof. K. K. Mahapatra, Dept. of ECE, NIT Rourkela.

M.Tech. Electronics and communication Engineering, National Institute of Science and Technology (NIST), Berhampur, Odisha, INDIA. Jul. 2008 (CGPA-8.58/10).

Thesis Title: Centralized MAC protocol for Wireless Sensor Network.

Supervisor: Prof. M. Suresh, NIST Berhampur

B.E. Electronics and Tele-Communication Engineering, Purushottam Institute of Engineering and Technology,Rourkela, Odisha, INDIA. July 2005 (70 %).

EXPERIENCE

NIT Arunachal Pradesh                                                                                         Jul. 2016 – Till date

GITAM University, Hyderabad Campus                                                           Jan. 2015 – May. 2016

National Institute of Technology, Rourkela (Researcher)                             Sep.2009 –Nov. 2014

Adya Systems and Software Pvt. Ltd., New Delhi (Software Engineer)     Jun. 2007 – May 2008

DRIEMS, Cuttack (Lecturer)                                                                               Apr. 2006 – Aug. 2006 

RESEARCH INTERESTS

  • VLSI
  • CMOS Circuit Techniques
  • Embedded Systems

SCHOLASTIC ACHIEVEMENTS

  • Received Institute Assistantship in M.Tech.
  • Receiving Institute Assistantship in Ph.D.

TECHNICAL SKILL

Programming Language: C, C++, JAVA, HTML, DHTML, Microprocessor Programming, MATLAB, VHDL

Software Tools:  OPNET Modeler, Matlab, P-Spice, T-Spice, H-Spice, Tanner tools, Cadence

VLSI Tools: Tanner tools, Xilinx, Synopsis, Cadence

CONFERENCE PUBLICATIONS

  1. Preetisudha Meher and Kamala Kanta Mahapatra, “High-Speed and Low-Noise Circuit Technique for CMOS Dynamic Logic”, International Conference on Artificial Intelligence and Soft Computing, Bhubaneswar, pp. 220-224, April 2011
  2. Preetisudha Meher and Kamala Kanta Mahapatra, “A Low-Power Circuit Technique for Dynamic CMOS Logic”, International conference on advanced computing, communication and technology, Chandigarh, pp. 892-895, May 2011
  3. Preetisudha Meher and Kamala Kanta Mahapatra, “A New Ultra Low-Power and Noise Tolerant Circuit Technique for CMOS Domino Logic”,International Conference on Computer Science and Informatics, Bhubaneswar, pp. 210-213, June 2011
  4. Preetisudha Meher and Kamala Kanta Mahapatra, “An Ultra-Low-Power and Noise Tolerant Circuit Technique for CMOS Domino Logic”, Proceedings of the ACEEE IDES Conference, Kerala, pp. 33-37, Sept. 2011
  5. Preetisudha Meher and Kamala Kanta Mahapatra, “A High-Performance Circuit Technique for CMOS Dynamic Logic”, Proceedings of theIEEE Recent Advances in Intelligent Computational Systems, Kerala, pp. 338-342, Sept. 2011
  6. Preetisudha Meher and Kamala Kanta Mahapatra, “Low-Power Circuit Technique for Domino CMOS Logic”,National Conference on VLSI Designs and Embedded Systems (NCVDES-2011), CEERI Pilani, Index-7A1, Oct. 2011.
  7. Preetisudha Meher and Kamala Kanta Mahapatra, “A New Low-Power Circuit Technique for Domino CMOS Logic”, IEEE Conference on Sustainable Utilization and Development in Engineering and Technology, Malaysia, Oct. 2011
  8. Preetisudha Meher and Kamala Kanta Mahapatra, “Ultra Low-Power and Noise Tolerant CMOS Dynamic Circuit Technique”,IEEE TENCON, Indonesia, pp.1175 – 1179 Nov. 2011
  9. Preetisudha Meher and Kamala Kanta Mahapatra, “High-Speed Circuit Technique for CMOS Dynamic Logic”,AICON 2012, Durg, India, pp.55-59, Jan. 2012
  10. Preetisudha Meher and Kamala Kanta Mahapatra, “A New Low-Power Circuit Technique for Domino CMOS Logic”,IEEE National Conference on Emerging Trends and Applications in Computer Science (NCETACS-2012), Shillong, Mar. 2012
  11. Preetisudha Meher and Kamala Kanta Mahapatra, “High-Speed and Low-Power Circuit Technique for CMOS Dynamic Logic” Recent Advances in Intelligent Computational Systems (RAICS-2012), Jaipur, Nov. 2012
  12. Preetisudha Meher and Kamala Kanta Mahapatra, “A Technique to Increase Noise Tolerance in Dynamic Digital Circuit”, IEEE Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PRIMEASIA-2012), Hyderabad, pp. 229 – 233, Dec 2012
  13. Preetisudha Meher and Kamala Kanta Mahapatra, “A Low-Power Circuit Technique for Domino CMOS Logic” IEEE ISSP-2013, Anand, pp. 256 – 261Mar 2013
  14. Preetisudha Meher, Kamala Kanta Mahapatra, “A High Speed Low Noise CMOS Dynamic Full Adder cell” IEEE2nd International Conferenceon Circuit, Control and Communication (Ccube-2013), Bangalore, Dec. 2013
  15. Preetisudha Meher, Kamala Kanta Mahapatra, “Low Power Noise Tolerant Domino 1-Bit Full Adder” IEEE2nd International Conferenceon Advances in Energy Conversion Technologies (ICAECT-2014), Manipal, Jan 2014
  16. Preetisudha Meher, Kamala Kanta Mahapatra, “A Low-Power CMOS Flip-Flop for High Performance Processors” IEEE TENCON-2014, Thailand, Oct 2014
  17. Preetisudha Meher, Kamala Kanta Mahapatra, “Noise Tolerant Current Mirror Footed Domino Logic” ICEECE-2014, Lonavala, Nov 2015

CONFERENCE PUBLICATIONS AFTER PHD

  1. Preetisudha Meher, Kamala Kanta Mahapatra, “Noise Tolerant and High Performance DominoLogic for High Speed Processor” IEEE ICCICCT-2015, Kanyakumari, Dec 2015
  2. Preetisudha Meher, Kamala Kanta Mahapatra, “High Performance Noise Tolerant Comparator Design for Arithmatic Circuits” ISPACS-2016, Thailand, Oct 2016
  3. Sapna R. Ghimiray, Preetisudha Meher and Manish Kumar, “Performance Analysis of a 1-bit comparator circuit using different domino logics”, IEEE 3rd International Conference On Emerging Electronics (ICEE) 2016
  4. Sapna R. Ghimiray, Preetisudha Meher and Manish Kumar, “A Leakage-Tolerant 16 – Bit Comparator Using Lector Technique Based Footless Domino Logic Circuit”, Proceedings of International Conference on Advanced Material Technologies (ICAMT)-2016
  5. Sapna R. Ghimiray, Preetisudha Meher and Manish Kumar, “A Leakage-Tolerant 16-bit Diode Footed Domino Comparator using Lector Technique”, IEEE Device and Integrated Circuit (DevIC) 2017
  6. Suraj Kumar saw, Madhusudan Maiti, Preetisudha Meher, S. K. Chakraborty “design and Implementation of TG based D Flip Flop for clock and data recovery Applications” IET International Conference on Soft Computing Techniques in Engineering and Technology (ASCTET) 24-26 Oct 2016
  7. Suraj Kumar saw, Madhusudan Maiti, Preetisudha Meher, S. K. Chakraborty “Study of Charge pump circuit with its non-ideal effects and its trade off “in 3rd Research Summit NIT Arunachal Pradesh, 4th-5th June 2017
  8. Sapna Rani Ghimiray, Preetisudha Meher, Pranab Kishore Dutta, “Energy Efficient, Noise Immune 4X4 Vedic Multiplier using semi-domino Logic style”, IEEE TENCON-2017 (Presented)
  9. Suraj Kumar saw, Preetisudha Meher, S. K. Chakraborty, “Design of High Frequency D Flip Flop Circuits for Phase Detector Application” IEEE TENCON-2017 (Presented)

JOURNAL PUBLICATIONS

  1. Preetisudha Meher and Kamala Kanta Mahapatra, “A low-power circuit technique for dynamic CMOS logic”, International Journal of Advances in Electronics and Electrical Engineering (IJAEEE), Vol-1, No-1, pp. 245-248, Aug-2011
  2. Preetisudha Meher and Kamala Kanta Mahapatra, “A New Ultra Low-Power and Noise Tolerant Circuit Technique for CMOS Domino Logic”, Interscience Journals (International Journal of Computer and Communication Technology), Vol-2, No-7, pp. 92-97, June 2011
  3. Preetisudha Meher and Kamala Kanta Mahapatra, “A Ultra Low-Power and Noise Tolerant Circuit Technique for CMOS Domino Logic”, ACEEE International Journal on Electrical and Power Engineering, Vol-01, No-03, pp.33-37, Dec 2011
  4. Preetisudha Meher and Kamala Kanta Mahapatra, “High-Speed and Low-Power Dynamic Logic Style”, International Journal of VLSI and Embedded Systems (IJVES), Vol-04, No-02, Mar 2013
  5. Preetisudha Meher and Kamala Kanta Mahapatra, “Modifications in CMOS Dynamic Logic Style: A Review Paper”, Journal of the Institution of Engineers – Springer “Series-B“ Volume 96, Issue 4, pp.391-399

JOURNAL PUBLICATIONS AFTER PHD

  1. Sapna R. Ghimiray, Preetisudha Meher and Manish Kumar,“Lector Based Leakage-Tolerant 16-bit Diode Footed Domino Comparator with Higher Noise Immunity”, International Journal of High Speed Electronics and Systems (IJHSES)- World Scientific
  2. Sapna R. Ghimiray, Preetisudha Meher and Manish Kumar,“A Leakage-Tolerant 16 – Bit Comparator Using Lector Technique Based Footless Domino Logic Circuit”, IOP Conference Series: Materials Science and Engineering- Institute of Physics. (Published)
  3. Sapna Rani Ghimiray, Preetisudha Meher and Pranab Kishore Dutta, “Stacked-single stage Ultra-Low Power, Noise Immune Domino technique for Ultra Deep Submicron Technology”, IET- Circuits, Devices and Systems (IET-CDS)-Institution of Engineering and Technology. (Under Review)

BOOK PUBLICATIONS

  1. Preetisudha Meher, Mangal Singh, “Centralized MAC Protocol for Wireless Sensor Network- A Search Work”, VDM Verlag Dr. Muller Publication, Germany, Aug. 2011
  2. Govind Prasad, Preetisudha Meher, “Design and statistical analysis of high performance SRAM cell”, VDM Verlag Dr. Muller Publication, Germany, Mar. 2014

BOOK PUBLICATIONS AFTER PHD

  1. Preetisudha Meher, “CMOS Circuit Techniques and Design Perspective”, VDM Verlag Dr. Muller Publication, Germany (At Press)

 WORKSHOP ORGANIZED

  1. Organized 5 days Workshop on “Recent Trends in VLSI Design” at NIT Arunachal Pradesh from 8th to 12th January, 2018 as CONVENER.
Faculty Information