Dr. Alak Majumder

Assistant Professor


  • PhD : National Institute of Technology (NIT), Arunachal Pradesh, India
  • M-Tech : National Institute of Technology (NIT), Agartala, India
  • BE  : Tripura Institute of Technology, Agartala, India

Research Interests: 

  • Analog & Digital IC, Low Power Techniques, Post-CMOS Technologies, Clock Distribution and Gating Logic, Current Mode Design, Wireline Communication Circuit

Academic Snapshots:

  • No. of Sponsored Projects    : 03 (Ongoing)
  • No. of Patents                       : 07 (Filed/Published) & 01 (Pending)
  • No. of Journals                     : 35 (Published)
  • No. of Conferences               : 42 (Published)
  • No. of Book Chapters           : 02 (Published)
  • No. of PhD Fellows              : 04 (Ongoing)
  • No. of M-Tech Thesis           : 17 (Awarded), 00 (Ongoing)
  • No. of B-Tech Thesis            : 12 (Awarded), 00 (Ongoing)

List of Patents: 

  • A. Kumar, S. Katiyar, A. Majumder, “System and Method for Enhancing Vehicle Security Through Driving License Verification”, Indian Patent Filed on 2nd November 2018, Application No – 201831041534. (Status: Published)
  • A. Kumar, N. Mishra, A. Majumder, “System and Method for Vehicle Identification and Ticketing System”, Indian Patent Filed on 5th September 2018, Application No – 201831033415. (Status: Published)
  • A. Majumder, P. Bhattacharjee, B. Nath, “Voltage Keeper Based Robust Flip-flop for Low Power Applications”, Indian Patent Filed on 11th December 2017, Application No – 201731044358. (Status: Published)
  • A. Majumder, A. Kumar, N. Mishra, A. Anand, “Motion Based Charger for a Portable Computing Device”, Indian Patent Filed on 3rd February 2017; Application No – 201731003981. (Status: Published)
  • A. Majumder, S. Ghosh, J. Goswami, A. Bibek, R. Shrivastawa, M. Kumari, ”Secure Payment Framework using Tokenization and Biometric Authentication”, Indian Patent Filed on 16th December 2016, Application No – 201631042923. (Status: Published)
  • A. Majumder, S. Ghosh, J. Goswami, B.K. Bhattacharyya, “A Digital Card Serving Identity & Payment Needs”, Indian Patent Filed on 10th February 2016; Application No – 201631004666. (Status: Published)
  • B.K. Bhattacharyya, A. Majumder, M. Kumari, D. Baral, “A Method to Reconstruct The Single Square Wave Pulse at the Receiving End Through the Lossy, Unmatched and Noisy Transmission Channel”, USPS Number: 7015 0640 0001 3896 6158, US Provisional Patent (USPTO), filed on 29th June 2015, Maricopa, Arizona, USA. (Status: Published)

Selected Recent Publications: 

  • M Maiti, A Paul, SK Saw, A Majumder, “Passive Element free Variation Aware Decision Circuit for 40 Gb/s CDR Application”, Microsystem Technologies, Springer, 2019.
  • M. Maiti, S.K. Saw, A.J. Mondal, A. Majumder, “A Hybrid Design Approach of PVT Tolerant, Power Efficient Ring VCO”, Ain Shams Engineering Journal, Elsevier, 2019.
  • SK Saw, SK Yadav, M Maiti, AJ Mondal, A Majumder, “A Design Approach of Higher Oscillation VCO made of CS Amplifier with Varying Active Load”, Microsystem Technologies, Springer 2019.
  • M. Maiti, S.K. Saw, V. Nath, A. Majumder, “A Power Efficient PFD-CP Architecture for High Speed Clock and Data Recovery Application”, Microsystem Technologies, Springer, 2019.
  • P. Bhattacharjee, D. Sarkar, A. Majumder, “A Variation Tolerant Data Dependent Clock Gating Approach for PSN Attenuated Low Power Digital IC”, Ain Shams Engineering Journal, Elsevier, 2019.
  • A. Majumder, M. Das, S.K. Saw, A.J. Mondal, and B.K. Bhattacharyya. “Variation Aware Design of 50-Gbit/s, 5.027-fJ/bit Serializer Using Latency Combined Mux-Dual Latch for Inter-Chip Communication.” IEEE Transactions on Circuits and Systems I: Regular Papers 66, no. 3 (2018): 1231-1244.

Find me on:

Faculty Information