Dr. Abir J Mondal

Assistant Professor

Campus Address

VLSI Design Laboratory, Department of Electronics & Communication Engineering

National Institute of Technology Arunachal Pradesh, Yupia

Email: abir@nitap.ac.in (Mob. 9436288558)

Academic Qualification

  • 2018 – Ph.DNational Institute of Technology Arunachal Pradesh
  • 2011 – Masters of Technology, Microelectronics & VLSI, National Institute of Technology Durgapur
  • 2007 – Bachelors of Engineering, Electronics & Communication EngineeringBurdwan University

Research Areas

  •  VLSI Circuit, Network on Chip

Subjects Taught

  • Digital Electronics & Logic Design
  • Signals & Systems
  • CMOS Digital Integrated Circuits
  • Digital Signal Processing
  • Mixed Signal IC Design

Academic and Administrative Responsibilities

  • Faculty CoordinatorStudent’s Technical & Cultural Activities, NIT Arunachal Pradesh from 01/01/2018 to till date.
  • Transport I/C, NIT Arunachal Pradesh from 01/01/2019 to till date

Research Interests

  • Design and analysis of I/O drivers
  • Modelling & analysis of Ring Oscillator/ VCO
  • Current mode circuits
  • Analog Circuit Optimization
  • Networks-on-Chip

Project

  • How to generate a Pulse Width Modulation and Simulation Methodology having extremely low duty cycle i.e. 10-6sec and period ranging from 1sec to a day from high performance process files, like 28nm or less for IoT sensor application, TEQIP III, 2019-2020.

Publications

Journals

  • Madhusudan Maity, Suraj Kumar Saw, Abir J Mondal and Alak Majumder, “A Hybrid Design Approach of PVT Tolerant, Power Efficient Ring VCO”, Elsevier Ain Shams Engineering Journal, November 2019. (10.1016/j.asej.2019.10.009)
  • Suraj Kumar Saw, Sandeep Kumar Yadav, Madhusudan Maity, Abir J Mondal and Alak Majumder, “A Design Approach of Higher Oscillation VCO made of CS Amplifier with Varying Load”, Springer Microsystem Technologies, May 2019. (10.1007/s00542-019-04500-5)
  • Abir J Mondal, J. Talukdar and Bidyut K. Bhattacharyya, “Variation Aware Design of Voltage Controlled Swing Ring Oscillator”, Taylor & Francis International Journal of Electronics, Vol. 107, Issue 1, pp. 99-124, July 2019. (10.1080/00207217.2019.1636307)
  • Alak Majumder, M. Das, Suraj K Saw, Abir J Mondal and Bidyut Kumar Bhattacharyya, “Variation Aware Design of 50-Gbit/s, 5.027-fJ/bit Serializer Using Latency Combined Mux-Dual Latch for Inter-Chip Communication”, IEEE Transactions on Circuits & Systems I- Regular (TCAS I), Vol. 66, Issue 3, pp. 1-14, March 2019. (10.1109/TCSI.2018.2877571)
  • Abir J. Mondal, Paromita Bhattcharjee, Pinaki Chakraborty and Bidyut K. Bhattacharyya, “MOS Amplifier Design Methodology for Optimum Performance”, Taylor & Francis IET Journal of Research. (10.1080/03772063.2018.1506267)
  • Paromita Bhattcharjee, Abir J. Mondal and Alak Majumder, “A Graphical Approach to Design and Optimization of MOS Amplifier”, Journal of Engineering Science & Technology, Vol. 13, Issue 1, pp. 265-279, Jan 2018.
  • Alak Majumder, Abir J. Mondal and Bidyut K. Bhattacharyya, “A 65nm Design of 0.6V/8.98μW PVT Aware Dynamic Analog Comparator for High Speed Data Reconstruction Applications, JOLPE, Vol. 13, Issue 3, pp. 1-9, September 2017. (10.1166/jolpe.2017.1496)
  • B. Nath, Alak Majumder, M. Das, Abir J Mondal, Pinaki Chakraborty and Bidyut Kumar Bhattacharyya, “Voltage Keeper Based 28.27 µW New Frequency Divider Circuit in 90 nm Technology for Gigascale SerDes Application”, IEEE VLSI Circuits and Systems Letter, Vol. 3, Issue 2, pp. 13-17, June 2017.
  • Abir J Mondal, Alak Majumder, Bidyut K. Bhattacharyya and Pinaki Chakraborty, “A Process Aware Delay Circuit with Reduce Impact of Input Switching at GHz Frequencies”, IEEE VLSI Circuits and Systems Letter, Vol. 3, Issue 2, pp. 6-12, June 2017.
  • Alak Majumder, Abir J Mondal and Bidyut K Bhattacharyya, “Threshold Adjustment of Receiver Chip to Achieve a Data Rate >66 Gbit/sec in Point to Point Interconnect”, Elsevier Integration-The VLSI Journal, Vol. 58, pp. 348-355, December 2016. (10.1016/j.vlsi.2016.11.004)
  • Abir J Mondal, Alak Majumder and Bidyut K. Bhattacharyya, “A Mathematical Formulation to Design and Implementation of a Low Voltage Swing Transceiver Circuit”, Elsevier Integration-The VLSI Journal, Vol. 58, pp. 356-368, December 2016. (10.1016/j.vlsi.2016.11.013)
  • P. L. Singh, A. Majumder, B. Chowdhury, A. J. Mondal, T. S. Shekhawat “Reducing Delay & Quantum Cost in the Novel Design of Reversible Memory Elements”, ELSEVIER 3rd International Conference on  Recent Trends in Computing (ICRTC), Procedia Computer Science, Vol. 57, pp. 232-240, March 2015. (10.1016/j.procs.2015.07.423)
  • A. Majumder, P. L. Singh, B. Chowdhury, A. J. Mondal, “Efficient Design & Analysis of N-bit Reversible Shift Registers”, ELSEVIER 3rd International Conference on  Recent Trends in Computing (ICRTC), Procedia Computer Science, Vol. 57, pp. 232-240, March 2015 . (10.1016/j.procs.2015.07.431)
  • Sandeep Kr Singh, Abir J Mondal, Alak Majumder, “Generation and Performance Evaluation of Reconfigurable Fault Tolerant Routing Algorithm for 2D-Mesh NoC”, ELSEVIER 3rd International Conference on  Recent Trends in Computing (ICRTC), Procedia Computer Science, Vol. 57, pp. 232-240, March 2015 . (10.1016/j.procs.2015.07.471)

Students

PhD

  • Design of Low Voltage High Speed Mux Latch in Nanometer CMOS Technologies for Use in Serializer, Mithilesh Kumar, 01/07/2019 to till date

M.Tech

  • Low Power and Almost Flat Frequency Ring Oscillator Build From Newly Designed Controlled Voltage Swing Inverter, Jagritee Talukdar, May 2018.
  • Process Variability Self Biased CMOS Differential Amplifier for the Design of Miller Opamp, Salam Jimkeli Singh, May 2018.
  • A Low Voltage Swing Circuit Topology for Simultaneous Bidirectional Signalling, Pankaj Saksena, May 2018.
  • Some Studies on Variation Tolerant Parallel Magnitude Comparator, Rituparna Paul, May 2018.
  • Design and Analysis of a Digitally Programmable Delay Circuit with Reduced Impact of Input Switching, Jaykishan Singh, May 2017.
  • Design and Analysis of MCML Circuits from Mathematical Framework to Implementation, Sabya Sachi Sahu, May 2017.
  • Design and Analysis of a Single Ended and Fully Differential Self Biased Cascoded Differential Amplifier, Kuruva Nyamathulla, May 2017.
  • A Constraint Driven Technique for MOS Amplifier Design, Paromita Bhattacharjee, May 2016.
  • A Method to Design a Comparator for Sampled Data Processing Applications, Rama Prasad Asharya, May 2016.
  • Multicore Processor Model Design for Virtual Platform, Rijita Poddar, May 2016.
  • A Method to Design a Multilevel Look-ahead Priority Encoder and Its Use in the Design of a Comparator Circuit, Ripu Daman Singh, May 2016.
  • Generation and Performance Evaluation of Fault Tolerant Routing Algorithm for 2D Mesh NoC, Sandeep Kumar Singh, May 2015.
  • A CORDIC Based Design Technique for Efficient Computation of DCT, Deboraj Muchahary, May 2015.
  • Low Pass Filter Design Using Various Modified Particle Swarm Optimization Techniques, Aman Deep Borah, May 2015.

B.Tech

  • Learning in Digital Gates, Manoj Singh & Nidhi Priya Singh, May 2018.
  • Study and Analysis of NoC Router Under Deterministic and Adaptive Routing, Jaise P Thomas & Nivesh Kumar Mishra, May 2018.
  • A Graphical Approach to Determine the Optimal Dimensions for a Given Specifications, Sarita Kumari, Pradeep Kumar & P Jaipal, May 2017.
  • Verilog Implementation of Error Detection Protocol in FIFO for NoC, Pradeep Singh Raghav & Tez Singh Shekhawat, May 2015.
  • Design and Realization of an Efficient FFT Algorithm Based on Optimized Butterfly Structure, Jumdo Gamlin, May 2015.
Faculty Information